High-Speed Counter," abbreviated as "HSC." One of its functions is to capture high-speed pulse signals in industrial environments. For example, in field applications where distance measurement is required, encoders are used. Encoders transmit distance information in the form of high-speed pulses. The frequency of these pulse signals is high, and their periods are shorter than the PLC's scan cycle. Ordinary input points are unable to accurately capture these signals, requiring the use of a high-speed counter.
Let's start by comparing the process of external physical signals entering the CPU's process image area through a digital channel with the process of entering through a high-speed counter channel.
In a typical signal input process, when a physical signal is generated, it first undergoes photoelectric isolation, then goes through digital filtering, followed by pulse capture, and finally enters the CPU's input process image area.
For high-speed counters, when a physical signal is generated, it undergoes photoelectric isolation, then digital filtering, and enters a dedicated high-speed counter chip. Pulse signals can be stored in the high-speed counter chip, preventing any loss. These pulse counts are sent into the CPU's input process image area during the PLC's scanning cycle. Of course, we can also directly access the physical address of the peripheral device to read the pulse counts. The high-speed counter chip is crucial for differentiating high-speed counters from regular input channels.
Siemens has taken into full consideration the demand for collecting high-speed pulse signals in the field. The CPU modules of the S7-1200 series PLC can support up to 6 groups of high-speed counters (HSC). The highest measurable frequency for single-phase pulses is 1MHz (1217C model), and the pulse frequency for A/B phase can reach a maximum of 80KHz. The following diagram shows the number of internally integrated HSCs in the 1200 series CPU when there is no signal board:
Any CPU can expand the number of HSCs by using a signal board. Depending on the combination of the CPU and the signal board, it can support a maximum of 6 HSCs (1211C supports up to 5 at most). As shown in the following diagram:
The types of measurement signals for high-speed counters include three categories: Pulse Counting, Frequency Measurement, and Axis of Motion. There are four operating modes: Single Phase, Two Phase, A/B Quadrature 1X, and A/B Quadrature 4X.
High-speed counters utilize the integrated input point resources of the PLC. When a specific input point is configured as a high-speed counter, it cannot be simultaneously used as a regular input point. The maximum input frequency supported by input points also varies. When selecting input points, it's essential to consider the frequency of the pulse signals in the field. The following diagram illustrates the maximum supported frequencies for various CPU-integrated input points under different operating modes:
The supported frequencies for each input point of the Signal board modules are as follows:
Depending on the operating mode, the required number of input points for HSC also varies. In single-phase mode, a minimum of one input point is needed, while in two-phase or A/B phase modes, at least two input points are required, as shown in the table below:
In the context, "[]" indicates optional, "CLK" represents the input clock signal; "CLK_UP" denotes the rising edge of the clock; "CLK_DN" represents the falling edge of the clock; "CLK_A" signifies the clock signal for phase A; "CLK_B" represents the clock signal for phase B; "DIR" indicates the direction of the signal input; "R" stands for external reset signal (reset signal is effective only for pulse counting).
The input point resources occupied by 6 sets of HSC in the CPU are shown in the table below:
Occupied signal board input point resources are listed in the table below:
All HSCs do not require setting start conditions. Once the hardware configuration is downloaded to the CPU, the configured high-speed counters automatically start.