This is not a rigorous academic paper, but rather a description of the author's understanding of EtherCAT distributed clock technology from the perspective of industrial application.As an EtherCAT application rather than a developer, many descriptions of the technology may be superficial.I am willing to work hard and apply what I have learned, and through the written word, I will expose errors and seek professional guidance. Through the written word, I will introduce application experiences and possibility analysis, covering a wide range of topics but with a basic understanding. I believe that all industrial control peers can understand and apply it in their own familiar fields to create more exciting and in-depth interpretations.
Abstract: This article elaborates on the principle of EtherCAT distributed clock technology, introduces the working mode of distributed clock components and the hardware products that implement this technology.By integrating theory with practice, it expounds the feasibility of implementing sub-microsecond clock synchronization on a general control platform, as well as the broad prospects this technology brings to the general manufacturing industry.This article also lists various industrial field applications to illustrate how to use EtherCAT distributed clock technology to achieve higher levels of automation.
0 Introduction
When it comes to clock synchronization, people often associate it with the fields of measurement and control and communication.In these fields, the accuracy of clock synchronization directly affects the system performance indicators and even the availability of the entire system, and expensive professional equipment must be used to achieve ns-level clock synchronization.With the development of technology, the demand for clock synchronization in the manufacturing field has also emerged.In order to improve production cycle and product quality, that is, to improve the speed and accuracy of single machine equipment, each action unit and sensor must coordinate actions without any deviation.And multiple controllers on a large production line must exchange data based on the same time reference in order to accurately coordinate actions.The coordinated actions of single machines and production lines respectively raise the requirements for clock synchronization within the control system and across systems.
However, even in the high-end manufacturing field, it cannot afford the price of professional equipment in the field of communication or measurement and control.Since the beginning of the 21st century, field-level communication technology has become increasingly mature and popular, and high-speed sensors and actuators have also been widely used for commercial purposes. However, the clock synchronization problem between different devices has not been well solved, and the clock synchronization accuracy has become a bottleneck restricting the further improvement of equipment performance in the general manufacturing field.EtherCAT bus and distributed clock technology based on EtherCAT have broken this bottleneck, achieving a synchronization accuracy of 0.1µs at the price level of general control systems, providing technical possibilities for a new level of general manufacturing.This article aims to introduce the principle of EtherCAT distributed clock technology and the equipment performance it can achieve in industrial field.
1. The principle of EtherCAT industrial Ethernet
a. Single master station design based on IEEE802.3 standard Ethernet communication
The EtherCAT bus is based on 100M Ethernet and uses a master-slave design.The hardware of the EtherCAT master station uses standard Ethernet cards, while the slave stations use specialized ASIC or FPGA chips to process EtherCAT data packets.
EtherCAT uses standard Ethernet frames (IEEE802.3), but adopts a single master design.Within the entire network, only the master has the authority to decide when to send data packets, while all slaves can only extract and insert their own data when waiting for data packets to pass through, as shown in the figure below:
The simplest EtherCAT slave chip has only an inlet (Port A) and an outlet (Port B).As shown in the figure
Some EtherCAT slave stations have 3 ports: entrance (Port A), exit 1 (Port B), and exit 2 (Port C).As shown in the figure:
Some EtherCAT slave stations have 4 ports: an entrance (Port A) and 3 exits (Port B, C, D).As shown in the figure:
No matter how many outlets there are, there is always one inlet, and the flow direction of data packets is always fixed.Data packets from the master station always pass from Port A through the EtherCAT Processing Unit to the first outlet, and if there are any, they are then passed to the second and third outlets, and then to the inlet Port A of the next slave station.After reaching the last slave station, the data packet that returns to the master station along the original path returns from the last outlet of the slave station to the inlet Port A of the master station, and then to the last outlet of the previous slave station.Because there is only one master station in an EtherCAT network, and the master station controls the initiation of all data packets, there is no data packet collision in the system.Therefore, as long as the network topology configuration is completed, the size of the process data of each slave station is determined, and the size of the entire data packet and its path through the network are also determined, so the communication time of the entire network is also determined.
b. Network node addressing and slave processing data packet mechanism
Normally, the master station identifies the slave station based on the physical connection order of the devices in the network.During the network initialization phase, the EtherCAT master station informs each slave station of the starting byte and length of its process data in the data packet.When the data packet passes through the slave interface chip, non-local data is directly released and passed through. Starting from the starting byte of the local data, the EtherCAT chip copies the specified number of bytes to its own input buffer, and inserts the data that has already been prepared in its own output buffer into the data packet.The entire data packet reaches the last slave station and then returns to the master station, and all slave stations extract the output data from the master station, while the master station also obtains the input data from all slave stations. This is a complete refresh process of process data.
Note that the EtherCAT master can configure whether the slave's Input and Output data use the same data segment or two data segments in the data packet.In Beckhoff's TwinCAT control software, the default is for the slave's Input and Output to use the same data segment. When the data packet enters the slave, the data segment contains the Output data sent from the master, and when it leaves, it contains the Input data sent back to the master. This setting allows for more efficient communication.If the Input and Output data lengths are different, a longer number of bytes will be reserved in the Frame.
c. Calculation of packet refresh time
The length of a data packet is determined by the Process Data of all slave stations in the packet.An Ethernet data packet is a minimum of 84 bytes, and any data less than 84 bytes will be padded with 84 bytes.Due to some common overhead in the EtherCAT Frame, a 84-byte packet can contain up to 18 bytes of process data.Considering that the packet must pass through each slave station twice before returning to the master station, the time for the packet to be transmitted twice at a fixed baud rate of 100Mbps on the network is its bus refresh time.Based on this principle, taking the data packet containing 1000 switch signals as an example, the calculation process is as follows:
The length of process data is 1000/8=125 bytes.
Packet length: 84-18+125=191Byte=191*8 Bit =1528 Bit
Bus refresh time: (1528 Bit/100,000,000Bps)*2 =15.28µs *2=30.56µs
Note that typical digital modules are purely output or output modules, not hybrid modules, so 1000 digital signals will allocate 125 bytes in the Frame.
Taking the EtherCAT packet containing 100 EtherCAT servo driver process data as an example, if the process data for each servo only includes a control word (2 bytes), a status word (2 bytes), a target position (4 bytes), and an actual position (4 bytes), the calculation process for its bus refresh time is as follows:
The length of process data is 100* (2+4) = 600 bytes.
Packet length: 84-18+600=1266Byte =671*8 Bit =5328 Bit
Bus refresh time: (5328 Bit/100,000,000Bps) *2=100.656µs
Note that only 6 bytes are allocated for one servo in the Frame, because according to the default settings of EtherCAT in Beckhoff's control software TwinCAT, the same data segment is used for the input and output of slave stations. Therefore, when the data packet enters the servo drive, the data segment stores the control word and target position, while when it exits, it stores the servo's status word and actual position.
The above two data of 30.56µs and 101.28µs are the source of the data in EtherCAT's official promotional materials that refreshing 1000 digital values requires 30µs and refreshing 100 servo axes requires only 100µs.In fact, depending on the type of slave station, whether it includes a distributed clock, whether clock synchronization is enabled, and the different settings of clock synchronization parameters, there may be an additional 8-12 bytes in the data packet for transmitting the synchronized clock value, as well as a corresponding one-bit tag for each slave station, which adds several microseconds to the refresh time, which is temporarily ignored.
The above calculation is only the theoretical time required for packet transmission. In practice, data packets experience short hardware delays when passing through each slave station.The slave station delay for a 100M Category 5e network cable interface is approximately 1µs, while the slave station delay for an EBus IO module is approximately 0.3µs. In control tasks with sub-millisecond timing requirements, if there are a large number of slave stations, this time can be significant and should be taken into account when calculating the refresh cycle.
d. One-stop access to IO modules
A EtherCAT network can connect up to 65,535 slaves, far exceeding the maximum number of slaves allowed by previous fieldbuses, which is 32, 64, 127, or 255.According to the previous calculation, the refresh time of EtherCAT is mainly affected by the number of process bytes of the slave, while the number of nodes has a minimal impact. If the hardware delay of data passing through the slave is not considered, the refresh time of the bus is almost the same for the same process data distributed on 10 slaves or 100 slaves.Most control system IO modules do not exceed 1000, so EtherCAT allows each IO module to occupy an address, and each IO module is an EtherCAT slave.
If an IO module with an EtherCAT interface is used, the communication between the backplane and the IO station and the controller uses the same protocol, and the data directly arrives from the controller to the IO module. This is the "one network to the end".This is something that other fieldbuses with a maximum of 255 slave stations cannot achieve.The implementation of "one network to the end" greatly reduces the transmission links between the field signals and the controller, making true high-speed response possible.
2. EtherCAT distributed clock technology
In the EtherCAT network, not only the master station has a clock, but also the slave stations can have local clocks.The master station clock usually comes from the CPU clock of the controller, and the slave stations use the 32-bit or 64-bit distributed clock built into the EtherCAT chip.Usually, the first slave clock connected to the master station is used as the system master clock (also known as the "reference clock"), which synchronizes the DC clocks of the master station and other slave stations.
When the system starts up, there is a certain difference between the local clock and the reference clock of each slave station, which is called the initial clock offset.During operation, due to the use of crystal oscillators by each slave station and other factors, their timing cycles will have slight differences, which is called clock drift.The delay of data frames propagating between slave stations is called transmission delay, including the delay of physical layer and link layer.In the distributed clock processing mechanism, these factors are compensated, so that the compensated slave DC time and the EtherCAT master time are synchronized, thus achieving clock synchronization of the entire system.The accuracy of EtherCAT distributed clock is 10ns, and the synchronization accuracy is about 15ns. Considering the hardware actions of slave stations, the actual input/output synchronization accuracy of each DC slave station in the network can be controlled within 100ns.
The synchronization accuracy can be controlled within 100ns. What is the significance in real-world applications?
Take high-speed CNC laser cutting equipment as an example.Because the power of the laser, the material and thickness of the cutting material will affect the cutting effect, the cutting speed should be selected according to different situations. If carbon steel is cut, a 1000W laser cutting machine is used. For carbon steel materials below 10mm, when the thickness of carbon steel is less than 2mm, the cutting speed can reach up to 8 meters per minute.When the thickness of carbon steel is 6mm, the cutting speed is about 1.6 meters per minute, and when the thickness of carbon steel is 10mm, the cutting speed is about 0.6-0.7 meters per minute.The linear velocity is related to the process and transmission. Taking the higher cutting speed of 8 meters per minute as an example, the position synchronization accuracy is calculated as follows:
Speed 8000mm/min=133mm/s
=0.133mm/ms=0.133um/µs
Synchronization time accuracy 100ns=0.1µs
Synchronization position accuracy 0.133*0.1µs=0.0133 um
The synchronization error of less than 0.02um is almost negligible compared to the position error caused by mechanical transmission, which is sufficient to meet the high-speed and high-precision processing requirements.
3. Distributed clock working mode of EtherCAT slave
The EtherCAT slave chip performs computation and data copying tasks sequentially and periodically, with a working cycle ranging from microseconds to milliseconds.The parameters of the distributed clock can be precisely set to refresh the output and read the input of each EtherCAT slave, ensuring that the input signal values received by the master from different slaves are obtained at the same time, and the output signals sent by the master to different slaves can also trigger the connected output circuits at the same time.
The EtherCAT slave with distributed clock can set its working mode:
Free Run, EtherCAT slave stations are not synchronized with the EtherCAT master station.The slave stations each trigger inputs or outputs independently, independent of the reference clock.
When the EtherCAT slave detects the passage of a data frame, it triggers the action of reading input or refreshing output.If there is output data in the data frame, it will trigger the SM2 event. If there is only input data in the data frame, it will trigger the SM3 event.
Synchronize with the SYNC event, EtherCAT slave determines the time to read input or refresh output according to the synchronization pulse SYNC0 or SYNC1 of the local DC clock.
The parameters of EtherCAT slave stations are stored in E2PROM, while the parameters for external access are encapsulated in the form of CanOpen object words.The working mode of the distributed clock can be determined by different combinations of parameters 0x1C32 and 0x1C33.
The following details the various working modes in turn:
a. Free Run mode: The start time of various tasks is determined by the LocalTimer Event of the slave station.Output is immediately triggered after the event is triggered, and input is obtained several minutes ahead of the Min Cycle Time.
The interval of the Local TimerEvent is consistent with the preset task cycle of the controller, but its triggering time is independent of the master station, so the read time of the input signal and the triggering time of the output circuit cannot be determined.
b. Synchronoµswith SM event mode (no Shift parameter)
The SM2/3 event triggered by the station when the message passes determines the start time of various tasks. The event is output immediately after triggering, and the input is obtained several minutes ahead of the Min Cycle Time.
The interval between SM2/3 events is consistent with the controller's preset task cycle, but its triggering time depends on when the data packet sent by the master station arrives at the local station.Using this method allows the output signal to trigger the output circuit as soon as possible, resulting in a refresh of the output state that is completed sooner for slave stations that are closer to the master station.
c. Synchronoµswith SM event mode (with Shift parameter)
The SM2/3 event triggered by the station when the message passes determines the start time of various tasks, and it is immediately output. After the event is triggered, the delay Shift Time is used to obtain the input.
Compared to the Synchronoµswith SM event mode without Shift parameter, the difference is that the delay between its input signal read time and SM event can be set, but it must be greater than the minimum cycle time required by the hardware.Since the time for the master station to send out data packets and the time for them to arrive at the local station will fluctuate, there is no synchronization between the slave stations in this way.
d. Synchronoµswith SYNC event mode (no Shift parameter)
The Sync0 event triggered by the slave DC clock determines the start time of various tasks. After the Sync0 is triggered, it is immediately output, and the input is obtained several minutes in advance based on the Min Cycle Time.It is independent of when the Frame passes through the slave.
Due to the clock synchronization mechanism of EtherCAT, the Sync0 signals of all slave DC clocks are triggered simultaneously, and the difference between the Sync0 signals of any two slave DC clocks does not exceed 100ns.Therefore, in this way, the difference in refresh time between the output circuits of any two DC slaves depends on their respective 1C32:06 (Calc+Copy Time) and 1C32:09 (Hardware Delay Time).If it is the same type of hardware, these times are almost the same.If it is different type of hardware, there will be differences.Similarly, the acquisition time of the input signal depends on the type of hardware, and if it is the same type of hardware, the time is the same, otherwise it is different.
e. Synchronoµswith SYNC event mode (with Shift parameter)
The Sync0 event triggered by the slave clock determines the start time of various tasks. Immediately after Sync0, memory is calculated and copied, but it does not drive hardware. Instead, it delays for a period of time before driving hardware.The delay time is the output Shift Time (0x1C32:03) minus the time required for hardware state switching.For input signals, the delay time is the Shift Time (0x1C33:03) after Sync0 minus the time required for hardware state acquisition, and then the state acquisition (Start Latch) action is triggered.As shown in the figure:
Compared to the Synchronoµswith SYNC event mode without the Shift parameter, this method can compensate for the differences in 1C32:06 (Calc+Copy Time) and 1C32:09 (Hardware Delay Time) due to different hardware models by adjusting the Shift Time, achieving strict consistency in the final output circuit refresh time of the target DC slave.Of course, the set 1C32:03 (Shift Time) must be greater than the sum of 1C32:06 (Calc+Copy Time) and 1C32:09 (Hardware Delay Time) required by the hardware.Similarly, the input delay time setting must also take into account the input conversion time required by the hardware.
Some EtherCAT slaves have two distributed clocks that can trigger two events: Sync0 and Sync1.Sync1 maintains synchronization with other DC slaves, and Sync0 is used to drive hardware output.Sync0 will trigger after a delay of Output Shift Time (0x1C32:03) - Hardware Delay after Sync1.Taking the output module EL2252 from Beckhoff as an example, when 0x1C32:01=3, the data packet sent by the master station should contain the specific time to trigger hardware refresh. After receiving the data packet from each communication cycle, the slave extracts this time and calculates it to obtain the exact value of Output Shift Time (0x1C32:03), which can control the fluctuation range of the output signal status switching time within 0.1µs.
f. Synchronoµswith SYNC event mode (with Shift parameter and sub-clock function)
Some EtherCAT slave devices have two distributed clocks that can trigger two events, Sync0 and Sync1.Setting the subdivision factor n, the cycle of Sync0 is the average value of the cycle of Sync1 divided into n equal parts.The clock of Sync0 is called the sub-clock. Within a Sync1 cycle, the output and input actions are triggered n times repeatedly, which is called Over Sampling.
The principle of each action is the same as the Synchronoµswith SYNC event mode (with Shift parameter).
As shown in the figure:
By superimposing the two clocks, n samples or outputs can be completed within one Sync1 cycle.Because the Sync1 cycle is equal to the control cycle, which is limited by the computing performance of the master CPU and the minimum task cycle of the control software, the Sync0 cycle that triggers hardware actions is limited by the conversion time of the slave hardware circuit and the copying time of the slave chip's computing.Therefore, in Beckhoff's EtherCAT slave products, the Sync1 cycle can only be as low as 50µs, while the Sync0 cycle can be as low as 1µs (digital module) or 10µs (analog module).
4. Sub-microsecond signal capture and precise control based on DC clock
a) Submicrosecond signal capture
Signal capture, also known as signal latching, is a common feature on encoder interface modules or servo drives. At the rising or falling edge of the input signal, the current encoder count value is immediately latched. In the next communication cycle, for example, several milliseconds later, the latched value is sent to the master station via the bus.The advantage of this method is precise capture, while the disadvantage is that the latching signal must be connected to the module where the signal is being latched.
Based on the distributed clock technology of EtherCAT, Beckhoff provides a digital input module EL1252 with functions.In the input data sent to the master station, it not only includes the current state of the channel, but also includes the rising and falling edge trigger time of the channel, which is called the TimeStamp.Since all DC clocks in the system are synchronized, the master station can use this ns-level to trace back to the process variable values of other DC slave stations at that time, such as counting, pressure, position, etc., which indirectly plays a role in signal capture.
The advantage of using the EtherCAT module EL1252 for signal capture is that it does not depend on the captured device. The captured signal is connected to the IO module instead of the captured device, and a captured signal can capture the process variable values of multiple devices simultaneously.The capture accuracy is comparable to hardware capture.The capture accuracy is not affected by the controller cycle, even for economical CPUs, such as control cycles of 10ms or longer, which can achieve sub-microsecond-level signal capture.
In the field of industrial manufacturing, the most typical application of sub-microsecond signal capture based on EtherCAT distributed clock technology is the software probe function, which replaces traditional hardware probe functions, such as color code capture on packaging printing equipment.As long as the color code sensor signal is connected to the DI module, as shown in the figure:
In the figure above, the valid sensor signal rising edge occurs between two sampling points of the controller, and the program can accurately calculate the corresponding Axis.Position value at that moment based on the signal rising edge sent back by the module.
In addition, the newly launched module EL1259 from Beckhoff also supports the recording of up to 10 rising edges within a control cycle, which can be used to count pulse counts, calculate pulse frequencies, and more.
b) Submicrosecond precision control
Corresponding to the sub-microsecond signal capture is the sub-microsecond precise control.
In traditional control, the hardware output state is refreshed once per control cycle.The usual work sequence is "reading-computing-outputting".For the same hardware system, the time of reading and outputting will not fluctuate greatly, but the computing time per control cycle will vary depending on the input conditions.Therefore, the response time of the hardware output actually fluctuates within one control cycle.To accurately control the action of a hardware, the usual practice is to directly use the output points provided by the computing chip.For example, the output point provided by the counter module is directly set without going through the controller after the counter is full.Another example is the origin signal of the servo driver. After capturing the signal, the current position of the servo driver is directly cleared.
This implementation requires not only that the output pin of the module be used directly for output, but also that the algorithm be implemented within the module.This means that users can only use the pre-designed output signals and input signals within the module.For example, servo drives typically reserve the origin, positive limit, negative limit, and position latch signals, where the origin and position latch signals have ns-level response, while the output reserves alarm, ready, and other signals, but the output is usually unrelated to position.
Beckhoff provides a time-stamped digital output module EL2252.The master station can set the precise time StartTime for switching the output channel state and the target state to be switched.Since all DC clocks in the system are synchronized, the master station can precisely control this ns-level time StartTime to control the output channel to switch states when the sampling signal from a DC slave station reaches the target value.
The most typical application of sub-microsecond precise control is digital output related to high-speed motion, including:
Cam output: CamSwitch, which can precisely control the opening and closing of a digital output channel at a specified position range on a high-speed motion axis.For example, using this signal to control the opening of a camera shutter is called "flying shot".
Flying cutting: CNC laser cutting equipment, in order to improve the efficiency of processing, instead of cutting one closed curve at a time, it cuts multiple line segments in different times to form a predetermined shape.For example, processing 10 parallel square holes with a side length of 10mm and a spacing of 15mm.Usually, the laser head is made to move in a relative straight line with the workpiece, and the light is turned on and off in sequence at a constant speed. Repeat 10 times, and 10 line segments are processed.In CNC laser cutting equipment, using a high-speed output module to control the laser head to turn on and off, processing a small segment of a straight line is called flying cutting.
The output module EL2252 with DC clock is used to achieve precise output, with a control accuracy of 100ns. However, there is no requirement for the control cycle, and even economical CPUs, such as control cycles of 10ms or longer, can achieve a control accuracy of 100ns.
5. Microsecond-level oversampling technology based on DC clock
The EtherCAT chip with oversampling function has two DC clocks, one for generating synchronous pulses with the same task cycle as the master station, and the other as a sub-clock to generate sub-pulses n times the frequency of the synchronous pulses.According to the time to trigger the acquisition input or refresh the output based on the sub-pulses, the actual sampling period is one-n of the control period.As shown in the figure:
The above figure shows that one analog signal is sampled 10 times in one PLC cycle. The actual sampling cycle (Measurement Cycle) is one-tenth of the control cycle (PLC cycle).
In oversampling technology, the maximum subdivision factor of Sync0 sub-pulse is limited by the operating frequency of the hardware circuit.At the same time, the subdivision factor is also limited by the minimum cycle of the module's circuit conversion: the minimum cycle of the oversampling digital module is 1µs, the minimum cycle of the oversampling analog and encoder circuit conversion is 10µs, and the minimum cycle of the oversampling power monitoring module is 100µs.Since the controller cycle is usually measured in ms, even the real-time core controlled by PC can only achieve a minimum control cycle of 50µs, and depends on high-performance CPU.Using Oversampling technology can achieve µs-level input and output cycles without requiring high-performance controllers.
Here are some examples of hardware and applications based on super-sampling technology:
a) Application of oversampling digital module
Based on the distributed clock technology of EtherCAT, Beckhoff provides digital modules with oversampling function, including input module EL1262 and output module EL2262. When the controller cycle is 1ms, a sampling frequency of 1MHz can be achieved.Similar tasks that can be completed by the module can be completed: probe input, cam output, flying shot, flying cutting, etc. The advantage is that it can be changed multiple times within one controller cycle. The disadvantage is that the theoretical value of time accuracy is not as good as the module.However, considering the overall system error, the time accuracy of 1µs and 100ns has almost no difference in factory applications.
In addition, the oversampled digital quantity module can also count the number of pulses in a specified time period and calculate the pulse frequency, such as in the wind power industry for measuring the speed of wind turbine blades, and in the beverage packaging industry for processing the pulse flowmeter signals of the filling system.
b) Application of microsecond analog over-sampling
Based on the distributed clock technology of EtherCAT, Beckhoff provides analog modules with oversampling function, including standard current/voltage signal input/output modules.At a controller cycle of 1ms, it can achieve a sampling or output frequency of 100kHz.This frequency level can be used in advanced manufacturing fields of factory automation, as well as in low-end measurement and control fields.For example, a simple electronic oscilloscope: each controller cycle has 100 values entering the controller, and writing controller code to process these data can obtain historical limit values, record curve storage and playback.It can also write algorithms for state analysis, such as collecting vibration data of key bearings, which can be used for preventive maintenance.
In addition, the module can also trace the instantaneous value of the analog signal device with DC clock, and the more dense the signal sampling points to be traced, the more accurate the traced value.Therefore, combined with oversampling technology, important analog signals can be traced more accurately, such as instantaneous pressure, instantaneous acceleration, instantaneous torque, etc. Combined with the EtherCAT driver or encoder module with distributed clock, the "analog-position" curve can also be reproduced in the controller, such as the pressure-position curve of injection molding machines, die casting machines, ceramic presses, and torque-position curve of tightening machines.
The oversampling output module can be used in analog signal generators to implement waveform generators within 50kHz, such as regular curves like square waves or sine waves, with adjustable amplitude, frequency, phase, offset, etc. It can also be combined with live recorded event playback to output irregular curves, simulate live working conditions, reproduce problems, and analyze fault causes.
c) Super-sampling power measurement module:
The oversampling power module is another application of Beckhoff's EtherCAT distributed clock technology.Traditional power measurement modules are used to replace power meters by directly measuring three-phase voltage and current to calculate power, frequency, energy consumption, and other electrical quantities.If the differences in the transmitter link are not considered, the three-phase voltage and current input channels of the oversampling power module can be understood as six oversampling analog signals.Relying on EtherCAT's high-speed transmission and dual DC clock oversampling technology, the power measurement module divides the functions of traditional power measurement instruments into two parts: the acquisition function of the original voltage and current signals is placed on the IO module, while the power factor, power, energy consumption calculation, and harmonic analysis functions are placed on the controller.The advantage of this is that it can fully utilize the computing power of the controller, allowing the PC to undertake more computing tasks and saving the cost of the IO part.On the other hand, PC computing also increases the transparency of power analysis, opening up the black box of power measurement.Electrical engineers can explore deeper data and perform more secondary analysis.
d) Super sampling encoder module
The oversampling encoder module EL5101-0011 is another application based on EtherCAT dual DC clocks. Its maximum subdivision factor can be set to 100.When the encoder is used as a position feedback device for motion control, it is sufficient to collect position data once per control cycle.So under what circumstances does it require 100 position data to be collected per cycle?Again, using the "position-pressure" curve in a die casting machine or injection molding machine as an example, the position pressure curve strictly affects the forming quality of the press, and the process of increasing pressure is extremely short, as short as tens of milliseconds.In order to obtain enough sampling points, if using a common encoder module, the control cycle must be set extremely short.Using an oversampling encoder module, it is possible to obtain a sampling frequency of 100kHZ under a control task cycle of 1ms, resulting in more realistic and refined results.This can be used to optimize control strategies and improve equipment performance.
6. EtherCAT DC clock synchronization across networks and systems
Cross-network clock synchronization refers to the synchronization of DC clocks on multiple EtherCAT networks on a control system.For example, two EtherCAT networks can be derived from two Ethernet cards on a controller, or up to eight EtherCAT networks can be extended from a Gigabit Ethernet card through a network multiplier CU2508.This synchronization does not require additional hardware, and can be achieved by setting the appropriate parameters in the master software.
Cross-system clock synchronization refers to the case where there are multiple control systems in a project that can be connected by network cables within 100 meters and each supports EtherCAT master stations. In this case, the bridge module EL6695 can be used to achieve clock synchronization between the controllers.If the control systems are not all EtherCAT master stations or the distance between these control systems is too far to be connected by network cables, an external clock module EL6688 needs to be added. When the clocks of all control systems are synchronized with external clock signals on the Internet, they will naturally be synchronized with each other.The synchronization accuracy of both methods is less than 1µs.
A typical application of cross-system clock synchronization is in the power system.For wind power generation, if the controllers in a wind farm are all EtherCAT controllers, they need clock synchronization between them, and an EtherCAT bridging module is used.If the clock synchronization is required between different control systems in the power grid, or between control systems in different regions, an external clock module EL6688 is added to the EtherCAT controller, and corresponding external clock hardware devices are also added to other systems.
7. Conclusion
The EtherCAT distributed clock technology breaks through the technological bottleneck of traditional control. The combination of a general PC control platform and an IO module with DC clock can achieve the sampling and control accuracy of specialized equipment.This reduces the threshold for advanced manufacturing in the field of factory automation, making high-speed and high-precision equipment more and more popular, and potentially raising the industry average to a new level.On the other hand, for users who are proficient in algorithms and analysis, they can obtain microsecond-level accuracy using general-purpose products without investing in expensive professional equipment, which enables them to verify and optimize their research results. Therefore, in industries such as measurement and control, vision, robotics, and other industries with software algorithms and analysis as core technologies, the EtherCAT distributed clock technology is increasingly becoming the basic technology of their hardware platforms.